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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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PD6710/22 ISA-to-PC-Card (PCMCIA) Controllers  
8.0  
I/O Window Mapping Registers  
The I/O windows must never include 3E0h and 3E1h.  
8.1  
I/O Window Control  
Register Name: I/O Window Control  
Index: 07h  
Register Per: socket  
Register Compatibility Type: 365  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Timing  
Register  
Select 1  
Timing  
Register  
Select 0  
Compatibility Auto-Size I/O I/O Window 1  
Compatibility Auto-Size I/O I/O Window 0  
Bit  
Window 1  
RW:0  
Size  
Bit  
Window 0  
RW:0  
Size  
RW:0  
RW:0  
RW:0  
RW:0  
RW:0  
RW:0  
Bit 0 I/O Window 0 Size  
0
1
8-bit data path to I/O Window 0.  
16-bit data path to I/O Window 0.  
When bit 1 below is 0, this bit determines the size of the data path to I/O Window 0. When bit 1 is  
1, this bit is ignored.  
Bit 1 Auto-Size I/O Window 0  
0
1
I/O Window 0 Size (see bit 0 above) determines the data path to I/O Window 0.  
The data path to I/O Window 0 will be determined based on -IOIS16 returned by the card.  
This bit determines the data path to I/O Window 0. Note that when this bit is 1, the -IOIS16 signal  
(see Table 2 on page 20) determines the width of the data path to the card.  
Bit 3 Timing Register Select 0  
0
1
Accesses made with timing specified in Timing Set 0.  
Accesses made with timing specified in Timing Set 1.  
This bit determines the access timing specification for I/O Window 0 (see Setup Timing 01on  
page 84).  
58  
Datasheet  
 
 
 
 
 
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