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SPD6722QCCE 参数 Datasheet PDF下载

SPD6722QCCE图片预览
型号: SPD6722QCCE
PDF下载: 下载PDF文件 查看货源
内容描述: ISA到PC卡( PCMCIA )控制器 [ISA-to-PC-Card (PCMCIA) Controllers]
分类和应用: 总线控制器微控制器和处理器PC
文件页数/大小: 138 页 / 837 K
品牌: INTEL [ INTEL ]
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PD6710/22 ISA-to-PC-Card (PCMCIA) Controllers  
Bit 5 Card Is I/O  
Memory Card Interface mode: card socket configured to support memory cards. Dual-function  
socket interface pins perform memory card-type interface functions.  
0
1
I/O Card Interface mode: card socket configured to support I/O/memory card-type interface  
functions. Dual-function socket interface pins perform I/O/memory card-type interface functions.  
This bit determines how dual-function socket interface pins will be used.  
Bit 6 Card Reset*  
0
1
The RESET signal to the card socket is set active (high for normal, low for ATA mode).  
The RESET signal to the card socket is set inactive (low for normal, high for ATA mode).  
This bit determines whether the RESET signal (see Table 2 on page 20) to the card is active or  
inactive. When the Card Enable bit (see Bit 7 Card Enableon page 50) is 0, the RESET  
signal to the card will be high-impedance. See Chapter 10 for further description of ATA mode  
functions.  
Bit 7 Ring Indicate Enable  
0
1
BVD1/-STSCHG pin is status change function.  
BVD1/-STSCHG pin is ring indicate input pin from card.  
This bit determines whether the -STSCHG input pin is used to activate the IRQ15 pin in  
conjunction with Misc Control 2, IRQ15 Is RI Out (see Bit 7 IRQ15 Is RI Outon page 74).  
This bit has no significance when the card socket is configured for memory card operation.  
7.5  
Card Status Change  
Register Name: Card Status Change  
Index: 04h  
Register Per: socket  
Register Compatibility Type: 365  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Battery  
Warning  
Change  
Battery Dead  
Or Status  
Change  
Card Detect  
Change  
Ready  
Change  
R:0  
R:0  
R:0  
R:0  
R:0  
R:0  
R:0  
R:0  
This register indicates the source of a management interrupt generated by the PD67XX.  
Note: The corresponding bit in the Management Interrupt Configuration register must be set to 1to  
enable each specific status change detection.  
52  
Datasheet  
 
 
 
 
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