3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
1.0
Introduction
This document contains the specifications for the 3 Volt Intel® Advanced+ Boot Block Flash
Memory (C3) Stacked-Chip Scale Package (Stacked-CSP) device. Stacked memory solutions are
offered in the following combinations: 32-Mbit flash + 8-Mbit SRAM, 32-Mbit flash + 4-Mbit
SRAM, 16-Mbit flash + 4-Mbit SRAM, or 16-Mbit flash memory + 2-Mbit SRAM.
1.1
Document Conventions
Throughout this document, the following conventions have been adopted.
• Voltages: “2.7 V” refers to the full voltage range, 2.7 V–3.3V; 12 V refers to 11.4 V to 12.6 V
• Main block(s): 32-Kword block
• Parameter block(s): 4-Kword block
1.2
Product Overview
The C3 Stacked-CSP device combines flash and SRAM into a single package, and provides secure
low-voltage memory solutions for portable applications. This memory family combines two
memory technologies, flash memory and SRAM, in one package. The flash memory delivers
enhanced security features, a block locking capability that allows instant locking/unlocking of any
flash block with zero-latency, and a 128-bit protection register that enable unique device
identification, to meet the needs of next generation portable applications. Improved 12 V
production programming can be used to improve factory throughput.
Table 1. Block Organization (x16)
Memory Device
Kwords
32-Mbit Flash
2048
1024
128
16-Mbit Flash
2-Mbit SRAM
4-Mbit SRAM
256
8-Mbit SRAM
512
NOTE: All words are 16 bits each.
The flash memory is asymmetrically-blocked to enable system integration of code and data storage
in a single device. Each flash block can be erased independently of the others up to 100,000 times.
The flash has eight 8-KB parameter blocks located at either the top (denoted by -T suffix) or the
bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols
for kernel code location. The remaining flash memory is grouped into 32-Kword main blocks. Any
individual flash block can be locked or unlocked instantly to provide complete protection for code
or data (see Section 5.7, “Flash Erase and Program Timings(1)” on page 31 for details).
The flash contains both a Command User Interface (CUI) and a Write State Machine (WSM). The
CUI serves as the interface between the microcontroller and the internal operation of the flash
memory. The internal WSM automatically executes the algorithms and timings necessary for
Datasheet
7
INTEL [ INTEL ]
