3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Flash Test Configuration Component Values Table
Test Configuration
C (pF)
L
2.7 V–3.3 V Standard Test
50
5.5
Flash AC Characteristics.
Table 13. Flash AC Characteristics—Read Operations
Density
Product
16-Mbit
-90
32-Mbit
-70
-110
-70
-90
#
Sym
Parameter
Unit
Voltage Range
Note
2.7 V - 3.3 V
Min Max Min Max Min Max Min Max Min Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
90
110
70
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
Address to Output Delay
F-CE# to Output Delay
F-OE# to Output Delay
F-RP# to Output Delay
F-CE# to Output in Low Z
F-OE# to Output in Low Z
F-CE# to Output in High Z
F-OE# to Output in High Z
70
70
90
90
110
110
30
70
70
90
90
AVQV
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
1
1
20
30
20
20
150
150
150
150
150
2
2
2
2
0
0
0
0
0
0
0
0
0
0
20
20
25
20
25
20
20
20
20
20
Output Hold from Address
F-CE#, or F-OE# Change,
Whichever Occurs First
R10
t
2
0
0
0
0
0
ns
OH
NOTES:
1. F-OE# may be delayed up to t
–t
after the falling edge of CE# without impact on t
ELQV
ELQV GLQV
2. Sampled, but not 100% tested.
3. See Figure 6, “AC Waveform: Flash Read Operations” on page 30.
4. See Figure 4, “Input/Output Reference Waveform” on page 28 for timing measurements and maximum allowable input slew
rate.
Datasheet
29
INTEL [ INTEL ]
