3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Any attempt to address Protection Program commands outside the defined protection register
address space will result in a status register error (program error bit SR.4 will be set to 1).
Attempting to program or to a previously locked protection register segment will result in a status
register error (program error bit SR.4 and lock error bit SR.1 will be set to 1).
3.8.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming Bit 1 of the
PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the
unique device number. This bit is set using the Protection Program command to program FFFDh to
the PR-LOCK location. After these bits have been programmed, no further changes can be made to
the values stored in the protection register. A Protection Program command to locked words will
result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1).
The protection register lockout state is not reversible.
Figure 3. Protection Register Memory Map
88H
4 Words
User Programmed
85H
84H
4 Words
Factory Programmed
81H
80H
PR-LOCK
0645_05
22
Datasheet
INTEL [ INTEL ]
