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PA28F016SC-120 参数 Datasheet PDF下载

PA28F016SC-120图片预览
型号: PA28F016SC-120
PDF下载: 下载PDF文件 查看货源
内容描述: 字节宽SmartVoltage FlashFile⑩ Memory系列4 ,8和16 MBIT [BYTE-WIDE SmartVoltage FlashFile⑩ MEMORY FAMILY 4, 8, AND 16 MBIT]
分类和应用:
文件页数/大小: 42 页 / 723 K
品牌: INTEL [ INTEL ]
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E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY  
Table 7. Status Register Definition  
WSMS  
7
ESS  
6
ECLBS  
5
PSLBS  
4
VPPS  
3
PSS  
2
DPS  
1
R
0
NOTES:  
SR.7 = WRITE STATE MACHINE STATUS  
Check RY/BY# or SR.7 to determine block erase,  
program, or lock-bit configuration completion.  
SR.6–0 are invalid while SR.7 = “0.”  
1 = Ready  
0 = Busy  
SR.6 = ERASE SUSPEND STATUS  
1 = Block Erase Suspended  
0 = Block Erase in Progress/Completed  
SR.5 = ERASE AND CLEAR LOCK-BITS  
STATUS  
If both SR.5 and SR.4 are “1”s after a block erase or  
lock-bit configuration attempt, an improper  
command sequence was entered.  
1 = Error in Block Erasure or Clear Lock-Bits  
0 = Successful Block Erase or Clear Lock-Bits  
SR.4 = PROGRAM AND SET LOCK-BIT  
STATUS  
1 = Error in Program or Set Master/Block  
Lock-Bit  
0 = Successful Program or Set Master/Block  
Lock-Bit  
SR.3 = VPP STATUS  
1 = VPP Low Detect, Operation Abort  
0 = VPP OK  
SR.3 does not provide a continuous indication of  
V
V
PP level. The WSM interrogates and indicates the  
PP level only after a block erase, program, or lock-  
bit configuration operation. SR.3 is not guaranteed  
to reports accurate feedback only when VPP  
VPPH1/2/3  
.
SR.2 = PROGRAM SUSPEND STATUS  
1 = Program Suspended  
0 = Program in Progress/Completed  
SR.1 = DEVICE PROTECT STATUS  
1 = Master Lock-Bit, Block Lock-Bit and/or  
RP# Lock Detected, Operation Abort  
0 = Unlock  
SR.1 does not provide a continuous indication of  
master and block lock-bit values. The WSM  
interrogates the master lock-bit, block lock-bit, and  
RP# only after a block erase, program, or lock-bit  
configuration operation. It informs the system,  
depending on the attempted operation, if the block  
lock-bit is set, master lock-bit is set, and/or  
RP# VHH  
.
SR.0 = RESERVED FOR FUTURE  
ENHANCEMENTS  
SR.0 is reserved for future use and should be  
masked out when polling the status register.  
21  
PRELIMINARY  
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