BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when VCC = VCC2/3 and VPP = VPPH1/2/3. If a
clear block lock-bits operation is attempted while
4.10 Clear Block Lock-Bits
Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
V
PP ≤ VPPLK, SR.3 and SR.5 will be set to “1.” In the
absence of this high voltage, the block lock-bits
content are protected against alteration. A suc-
cessful clear block lock-bits operation requires that
the master lock-bit is not set or, if the master lock-
bit is set, that RP# = VHH. If it is attempted with the
master lock-bit set and RP# = VIH, SR.1 and SR.5
will be set to “1” and the operation will fail. A clear
block lock-bits operation with VIH < RP# < VHH
produce spurious results and should not be
attempted.
and VHH on the RP# pin. See Table 6 for
summary of hardware and software write protection
options.
a
Clear block lock-bits operation is initiated using a
two-cycle command sequence.
A clear block
lock-bits setup is written first. Then, the device
automatically outputs status register data when
read (see Figure 12). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
If a clear block lock-bits operation is aborted due to
VPP or VCC transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-
bits is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
Table 6. Write Protection Alternatives
Block
Master
Operation
Block Erase or
Program
Lock-Bit Lock-Bit
RP#
Effect
0
VIH or VHH Block Erase and Program Enabled
X
1
VIH
Block is Locked. Block Erase and Program Disabled
VHH
Block Lock-Bit Override. Block Erase and Program
Enabled
Set Block
Lock-Bit
0
1
X
X
VIH or VHH Set Block Lock-Bit Enabled
VIH
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
VHH
Master Lock-Bit Override. Set Block Lock-Bit
Enabled
Set Master
Lock-Bit
X
X
VIH
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
VHH
Clear Block
Lock-Bits
0
1
X
X
VIH or VHH Clear Block Lock-Bits Enabled
VIH
Master Lock-Bit is Set. Clear Block Lock-Bits
Disabled
VHH
Master Lock-Bit Override. Clear Block Lock-Bits
Enabled
20
PRELIMINARY
INTEL [ INTEL ]
