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PA28F016SC-120 参数 Datasheet PDF下载

PA28F016SC-120图片预览
型号: PA28F016SC-120
PDF下载: 下载PDF文件 查看货源
内容描述: 字节宽SmartVoltage FlashFile⑩ Memory系列4 ,8和16 MBIT [BYTE-WIDE SmartVoltage FlashFile⑩ MEMORY FAMILY 4, 8, AND 16 MBIT]
分类和应用:
文件页数/大小: 42 页 / 723 K
品牌: INTEL [ INTEL ]
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E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY  
4.1  
Read Array Command  
4.3  
Read Status Register  
Command  
Upon initial device power-up and after exit from  
deep power-down mode, the device defaults to read  
array mode. This operation is also initiated by  
writing the Read Array command. The device  
remains enabled for reads until another command  
is written. Once the internal WSM has started a  
block erase, program or lock-bit configuration, the  
device will not recognize the Read Array command  
until the WSM completes its operation unless the  
WSM is suspended via an Erase Suspend or  
Program Suspend command. The Read Array  
command functions independently of the VPP  
The status register may be read to determine when  
a block erase, program, or lock-bit configuration is  
complete and whether the operation completed  
successfully. It may be read at any time by writing  
the Read Status Register command. After writing  
this command, all subsequent read operations  
output data from the status register until another  
valid command is written. The status register  
contents are latched on the falling edge of OE# or  
CE#, whichever occurs first. OE# or CE# must  
toggle to VIH to update the status register latch. The  
Read Status Register command functions  
independently of the VPP voltage. RP# can be VIH  
voltage and RP# can be VIH or VHH  
.
or VHH  
.
4.2  
Read Identifier Codes  
Command  
4.4  
Clear Status Register  
Command  
The identifier code operation is initiated by writing  
the Read Identifier Codes command. Following the  
command write, read cycles from addresses shown  
in Figure 5 retrieve the manufacturer, device, block  
lock configuration and master lock configuration  
codes (see Table 5 for identifier code values). To  
terminate the operation, write another valid  
command. Like the Read Array command, the  
Read Identifier Codes command functions  
independently of the VPP voltage and RP# can be  
VIH or VHH. Following the Read Identifier Codes  
command, the subsequent information can be read.  
Status register bits SR.5, SR.4, SR.3, and SR.1 are  
set to “1”s by the WSM and can only be reset by  
the Clear Status Register command. These bits  
indicate various failure conditions (see Table 7). By  
allowing system software to reset these bits,  
several operations (such as cumulatively erasing or  
locking multiple blocks or writing several bytes in  
sequence) may be performed. The status register  
may be polled to determine if an error occurred  
during the sequence.  
Table 5. Identifier Codes  
To clear the status register, the Clear Status  
Register command (50H) is written. It functions  
independently of the applied VPP voltage. RP# can  
be VIH or VHH. This command is not functional  
during block erase or program suspend modes.  
Code  
Address  
Data  
Manufacturer Code  
000000  
000001  
000001  
89  
A7  
A6  
AA  
4 Mbit  
8 Mbit  
Device Code  
16 Mbit 000001  
4.5  
Block Erase Command  
Block Lock Configuration  
Block Is Unlocked  
Block Is Locked  
XX0002(1)  
Erase is executed one block at a time and initiated  
by a two-cycle command. A block erase setup is  
written first, followed by a block erase confirm. This  
command sequence requires appropriate se-  
quencing and an address within the block to be  
erased (erase changes all block data to FFH).  
Block preconditioning, erase, and verify are handled  
internally by the WSM (invisible to the system).  
After the two-cycle block erase sequence is written,  
the device automatically outputs status register  
data when read (see Figure 67). The CPU can  
detect block erase completion by analyzing the  
RY/BY# pin or status register bit SR.7.  
DQ0 = 0  
DQ0 = 1  
DQ1–7  
Reserved for Future Use  
Master Lock Configuration  
Device Is Unlocked  
Device Is Locked  
000003  
DQ0 = 0  
DQ0 = 1  
DQ1–7  
Reserved for Future Use  
NOTE:  
1. X selects the specific block lock configuration code to  
be read. See Figure 6 for the Device Identifier Code  
Memory Map.  
17  
PRELIMINARY  
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