28F640L30, 28F128L30, 28F256L30
Figure 25. Reset Operation Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
read mode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
12.5
AC Test Conditions
Figure 26. AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
NOTE: AC test inputs are driven at V
for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends
CCQ
at V
/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at V = V Min.
CCQ
CC CC
Figure 27. Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
NOTES:
1. See the following table for component values.
2. Test configuration component value for worst case speed conditions.
3. C includes jig capacitance
L
.
Table 16. Test configuration component value for worst case speed conditions
Test Configuration
2.0 V Standard Test
CL (pF)
R1 (Ω)
R2 (Ω)
30
22K
22K
Datasheet
65
INTEL [ INTEL ]
