LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 54. Interrupt Enable Register (Address 18)
Bit
Name
Reserved
Description
Write as 0; ignore on read.
Type 1
Default
18.15:9
18.8
R/W
R/W
N/A
0
Reserved
Write as 0; ignore on read.
Mask for Auto Negotiate Complete
18.7
18.6
18.5
18.4
ANMSK
R/W
R/W
R/W
R/W
0
0
0
0
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Speed Interrupt
SPEEDMSK
DUPLEXMSK
LINKMSK
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Duplex Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Link Status Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
18.3
18.2
Reserved
Reserved
Write as 0, ignore on read.
Write as 0, ignore on read.
R/W
R/W
0
0
1 = Enable interrupts.
0 = Disable interrupts.
18.1
18.0
INTEN
TINT
R/W
0
1 = Force interrupt on MDINT.
0 = Normal operation.
R/W
0
1. R/W = Read /Write
Datasheet
83
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
