LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 52. Configuration Register (Address 16, Hex 10)
Bit
Name
Description
Type 1
Default
16.15 Reserved
Write as zero, ignore on read.
R/W
0
Force Link Pass
1 = Force Link pass
0 = Normal operation
16.14
R/W
R/W
0
0
1 = Disable Twisted Pair transmitter
0 = Normal Operation
16.13 Transmit Disable
Bypass Scrambler
16.12
1 = Bypass Scrambler and Descrambler
0 = Normal Operation
R/W
R/W
R/W
0
0
0
(100BASE-TX)
16.11 Reserved
Ignore
Jabber
16.10
1 = Disable Jabber Correction
0 = Normal operation
(10BASE-T)
SQE
16.9
1 = Enable Heart Beat
0 = Disable Heart Beat
R/W
R/W
0
0
(10BASE-T)
1 = Disable TP loopback during half-duplex
operation
TP Loopback
16.8
(10BASE-T)
0 = Normal Operation
CRS Select
16.7
1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation
R/W
R/W
1
(10BASE-T)
1 = Enable Sleep Mode
0 = Disable Sleep Mode
16.6
16.5
Sleep Mode
Note 2
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
CRS is asserted.
PRE_EN
R/W
0
00 = 3.04 seconds
01 = 2.00 seconds
10 = 1.04 seconds
16.4:3
Sleep Timer
R/W
R/W
00
1
Fault Code
Enable
1 = Enable FEFI transmission
0 = Disable FEFI transmission
16.2
16.1
16.0
1 = Enable alternate auto negotiate next page
Alternate NP
feature
feature.
R/W
R/W
0
0 = Disable alternate auto negotiate next page
feature
1 = Select fiber mode.
0 = Select TP mode.
Fiber Select
Note 3
1. R/W = Read /Write
LHR = Latches High on Reset
2. The default value of Register bit 16.6 is determined by the state of the SLEEP pin 32/H7.
3. The default value of Register bit 16.0 is determined by pin 26/G2 (SD/TP).
Datasheet
81
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
