LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Table 47. Auto-Negotiation Advertisement Register (Address 4)
Bit
Name
Description
Type 1
Default
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
4.15
4.14
4.13
4.12
4.11
Next Page
Reserved
R/W
RO
0
0
0
0
0
Ignore.
1 = Remote fault.
Remote Fault
R/W
R/W
R/W
0 = No remote fault.
Reserved
Ignore.
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
4.10
Pause
R/W
Note 2
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT971A does not support 100BASE-T4 but
allows this bit to be set to advertise in the auto-
negotiation sequence for 100BASE-T4 operation. An
external 100BASE-T4 transceiver could be switched in
if this capability is desired.)
4.9
100BASE-T4
R/W
0
100BASE-TX
full-duplex
1 = Port is 100BASE-TX full-duplex capable.
0 = Port is not 100BASE-TX full-duplex capable.
4.8
4.7
R/W
R/W
Note 3
Note 3
1 = Port is 100BASE-TX capable.
100BASE-TX
0 = Port is not 100BASE-TX capable.
1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T full-duplex capable.
Note 3
Note 3
10BASE-T
full-duplex
4.6
4.5
R/W
R/W
1 = Port is 10BASE-T capable.
0 = Port is not 10BASE-T capable.
10BASE-T
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future auto-negotiation
development.
Selector Field,
S<4:0>
4.4:0
R/W
00001
<11111> = Reserved for future auto-negotiation
development.
Unspecified or reserved combinations should not be
transmitted.
1. R/W = Read/Write
RO = Read Only
2. The default setting of Register bit 4.10 (PAUSE) is determined by pin 33/H8 at reset.
3. Default values of Register bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to
Table 9 for details.
Datasheet
77
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
