LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
In the receive direction, the PCS layer performs the opposite function, substituting two preamble
nibbles for the SSD.
3.7.3.1.2 Dribble Bits
The LXT971A handles dribbles bits in all modes. If one to four dribble bits are received, the nibble
is passed across the MII, and padded with ones if necessary. If five to seven dribble bits are
received, the second nibble is not sent to the MII bus.
Figure 20. Protocol Sublayers
MII Interface
LXT971A
PCS
Encoder/Decoder
Sublayer
Serializer/De-serializer
PMA
Link/Carrier Detect
Sublayer
PECL Interface
PMD
Scrambler/
De-scrambler
Fiber Transceiver
Sublayer
100BASE-TX
100BASE-FX
Datasheet
39
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
