LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 9. Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern
Bit
Name
Function
EPAT0
EPAT1
Selected
1 = Enable Transmit All Ones
0 = Disable Transmit All Ones
4
ETAOS
5
6
EPAT0
EPAT1
Selects internal data pattern transmission. See
right hand section of table for codes.
1 = Reset device states and clear all registers.
0 = Reset complete.
7
RESET
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Table 10. Control Register #3 Read/Write, Address (A7-A0) = x010010x
Bit
Name
Description
1 = Disable jamming of Elastic Store read out clock (1/ bit-time adjustment for over/underflow).
8
0
ESJAM
0 = Enable jamming of Elastic Store read out clock
1 = Center ES pointer for a difference of 16 or 32, depending on depth (clears automatically).
0 = Centering completed
1
ESCEN
1 = Set elastic store depth to 64 bits.
0 = Set elastic store depth to 32 bits.
2
3
4
ES64
-
Reserved. Set to 0 for normal operation.
1 = Configure receiver equalizer for monitor mode application (DSX-1 monitor).
0 = Configure receiver equalizer for normal mode application
EQZMON
1 = Start Built-In Self Test.
5
6
7
SBIST
-
0 = Built-In Self Test complete.
Reserved. Set to 0 for normal operation.
1 = Set bandwidth of jitter attenuation loop to 6 Hz.
0 = Set bandwidth of jitter attenuation loop to 3 Hz.
JA6HZ
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
Function1
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
0
1
2
CLOS
-
Reserved. Set to 1 for normal operation.
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
CAIS
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
3
4
CQRSS
-
Reserved. Set to 1 for normal operation.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
26
Datasheet
INTEL [ INTEL ]
