T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
Function1
1 = Clear/Mask Driver Failure Monitor Open interrupt.
5
CDFMO
0 = Enable Driver Failure Monitor Open interrupt.
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
6
7
CESO
CESU
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 12. Transition Status Register Read Only, Address (A7-A0) = x010100x
Bit
Name
Function
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
0
1
2
TLOS
-
Reserved. Ignore.
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
TAIS
1 = QRSS has changed since last clear QRSS interrupt occurred1.
0 = No change in status.
3
4
5
TQRSS
-
Reserved. Ignore.
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
TDFMO
1 = ES overflow status sticky bit2.
0 = No change in status.
6
7
ESOVR
ESUNF
1 = ES underflow status sticky bit2.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit
Name
Function
1 = Loss of Signal occurred.
0
1
2
LOS
-
0 = Loss of Signal did not occur.
Reserved. Ignore.
1 = Alarm Indicator Signal detected.
AIS
0 = Alarm Indicator Signal not detected.
1 = Quasi-Random Signal Source pattern detected.
0 = Quasi-Random Signal Source pattern not detected.
3
4
QRSS
-
Reserved. Ignore.
Datasheet
27
INTEL [ INTEL ]
