LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
ZEROV detection is enabled when the HDB3 encoders/decoders are enabled. This requires
CR1.ENCENB = 1, also CR1.EC3:1 = 000, which establishes E1 operation. To select ZEROV
detection, set bit CR4.ZEROV = 1.
2.5.4
Alarm Condition Monitoring
Loss of Signal
2.5.4.1
The LXT351 Loss of Signal (LOS) monitor function is compatible with ITU G.775 and ETSI
300233. The receiver LOS monitor loads a digital counter at the RCLK frequency. The count
increments with each received 0 and the counter resets to 0 on receipt of a 1. When the count
reaches “n” 0s, bit PSR.LOS is set to ‘1’, and the MCLK replaces the recovered clock at the RCLK
output in a smooth transition. For T1 operations, the number of 0s, n = 175, and for E1 operations,
n = 32. For both T1 and E1 operation, “n” can be set to 2048 by setting bit CR4.LOS2048 = 1.
For T1 operation, when the received signal has 12.5% 1s (16 marks in a sliding 128-bit period, with
fewer than 100 consecutive 0s), bit PSR.LOS = 0 and the recovered clock replaces MCLK at the
RCLK output in another smooth transition.
For E1 operation, the LOS condition is cleared when the received signal has 12.5% 1s density (four
1s in a sliding 32-bit window with fewer than 16 consecutive 0s). In E1 operation, the out-of-LOS
criterion can be modified from 12.5% marks density to 32 consecutive marks by setting bit
CR4.COL32CM = 1.
During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar
mode). Bit PSR.LOS = 1 to indicate LOS condition, and can generate an interrupt to the host
controller if so programmed.
2.5.4.2
Alarm Indication Signal Detection
The receiver detects an AIS pattern when it receives fewer than three 0s in any string of 2048 bits.
The device clears the AIS condition when it receives three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
2.5.4.3
2.5.4.4
Driver Failure Open Mode
The DFM Open (DFMO) bit is available in the Performance Status Register to indicate an open
condition on the lines. DFMO can generate an INT to the host controller. The Transition Status
Register bit TDFMO indicates a transition in the status of the bit. Writing a 1 to ICR.CDFMO will
clear or mask the interrupt.
Elastic Store Overflow/Underflow
When the bit count in the Elastic Store (ES) is within two bits of overflowing or underflowing the
ES adjusts the output clock by 1/8 of a bit period. The ES provides an indication of overflow and
underflow via bits TRS.ESOVR and TSR.ESUNF. These are sticky bits and will stay set to 1 until
the host controller reads the register. These interrupts can be cleared or masked by writing a 1 to the
bits ICR.CESO and ICR.CESU, respectively.
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Datasheet
INTEL [ INTEL ]
