LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
3.0
Register Definitions
The LXT351 contains five read/write and two read-only registers that are accessible via the parallel
port. Table 5 lists the LXT351 register addresses. Only bits A6 through A1 of the address byte are
valid (the address decoder ignores bits A7 and A0) while A0 functions as the read/write (R/W) bit.
Table 6 identifies the name of each register bit. Table 7 through Table 14 describe the function of
the bits in each register.
Note that upon power-up or reset, all registers are cleared to 0.
Table 5. Register Addresses
Register
Name
Address1, 2
A7 - A1
Abbr
Control #1
Control #2
CR1
CR2
CR3
ICR
x010000
x010001
x010010
x010011
x010100
x010101
x010111
Control #3
Interrupt Clear
Transition Status
Performance Status
Control #4
TSR
PSR
CR4
1. x = don’t care
2. Address A0 is the read/write (R/W) bit.
Table 6. Register and Bit Summary
Register
Bit
Name
Type
7
6
5
4
3
2
1
0
Control #1
Control #2
Control #3
CR1 R/W
CR2 R/W
CR3 R/W
JASEL1
RESET
JA6HZ
CESU
JASEL0
EPAT1
ENCENB UNIENB
reserved1
EC3
EC2
EC1
EPAT0
SBIST
ETAOS
EQZMON reserved1
reserved1 EALOOP ELLOOP ERLOOP
reserved1
ES64
CAIS
ESCEN
ESJAM
CLOS
Interrupt Clear ICR R/W
Transition
CESO
CDFMO reserved2
CQRSS
TQRSS
reserved2
TSR
R
ESUNF
ESOVR
BIST
TDFMO
reserved1
reserved1
TAIS
reserved1
TLOS
Status
Performance
Status
PSR
R
reserved1
DFMO
QRSS
AIS
reserved1
ZEROV
LOS
Control #4
CR4 R/W reserved1 reserved1 reserved1 reserved1 COL32CM LOS2048
CODEV
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in
read only registers.
2. Write a 1 to this bit for normal operation.
24
Datasheet
INTEL [ INTEL ]
