1-Gbit P30 Family
Figure 36.
Write State Machine—Next State Table (Sheet 3 of 6)
Chip
Command Input to Chip and resulting
Next State
Lock
Block
Confirm (8) Confirm
Lock-Down
OTP
Setup (4)
Write RCR
Block Address
Illegal Cmds or
BEFP Data (1)
Block
WSM
Operation
Completes
(8)
9
Current Chip
State (7)
Confirm
(?WA0)
(8)
(C0H)
(01H)
(2FH)
(03H)
(XXXXH)
(all other codes)
OTP
Setup
Ready
Ready
Ready
(Lock
Error)
Ready
(Lock
Block)
Ready
(Lock Down
Blk)
Ready
(Set CR)
N/A
Ready (Lock Error)
Lock/CR Setup
Setup
OTP Busy
OTP
Busy
Ready
N/A
Word Program Busy
Word Program Busy
Setup
Ready
Busy
Word
Program
Word Program Suspend
BP Load 1
Suspend
Setup
BP Load 2
Ready (BP Load 2 BP Load 2
BP Load 1
BP Confirm if
Data load into
Program Buffer is
complete; ELSE
BP Load 2
N/A
BP Confirm if Data load into Program Buffer is
complete; ELSE BP load 2
Ready
BP Load 2
BP
Ready (Error)
(Proceed if
unlocked or lock
error)
BP
Confirm
Ready (Error)
Ready (Error)
BP Busy
BP Busy
BP Suspend
Ready (Error)
Erase Busy
Ready
N/A
BP
Suspend
Setup
Busy
Ready
Erase
Suspend
Erase Suspend
N/A
April 2005
80
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
INTEL [ INTEL ]
