1-Gbit P30 Family
Figure 38.
Write State Machine—Next State Table (Sheet 5 of 6)
Output Next State Table
Output
Command Input to Chip and resulting
Mux Next State
BE Confirm,
P/E
Resume,
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
Clear
Status
Register (5)
Lock, Unlock,
Lock-down,
Word
Program
Setup (3,4)
Program/
Erase
Suspend
Read
Erase
Read
Status
Read
ID/Query
BP Setup
(E8H)
(2)
Array
Setup (3,4)
CR setup (4)
ULB Confirm
Current chip state
(8)
(FFH)
(10H/40H)
(20H)
(30H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
BEFP Setup,
BEFP Pgm & Verify
Busy,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
Status Read
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
Status Read
Status
Read
OTP Busy
Ready,
Erase Suspend,
BP Suspend
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
Output mux
does not
change.
Read Array
Status Read
Output does not change.
Status Read
Status Read
ID Read
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Suspend
April 2005
82
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
INTEL [ INTEL ]
