Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
The memory pipe has eight stages:
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
. . . then finish with the following memory stages:
• Data Cache 1
• Data Cache 2
• Data Cache Writeback
The MAC pipe has six to nine stages:
• The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
. . . then finish with the following MAC stages:
• MAC 1
• MAC 2
• MAC 3
• MAC 4
• Data Cache Writeback
The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3, and/or
MAC 4 are bypassed.
Deep pipes promote high instruction execution rates only when a means exists to successfully
predict the outcome of branch instructions. The branch target buffer provides such a means.
2.2.2
Branch Target Buffer (BTB)
Each entry of the 128-entry BTB contains the address of a branch instruction, the target address
associated with the branch instruction, and a previous history of the branch being taken or not
taken. The history is recorded as one of four states:
• Strongly taken
• Weakly taken
• Weakly not taken
• Strongly not taken
The BTB can be enabled or disabled via Coprocessor 15, Register 1.
When the address of the branch instruction hits in the BTB and its history is strongly or weakly
taken, the instruction at the branch target address is fetched. When its history is strongly or weakly
not-taken, the next sequential instruction is fetched. In either case the history is updated.
Data associated with a branch instruction enters the BTB the first time the branch is taken. This
data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when
present).
Successfully predicted branches avoid any branch-latency penalties in the super pipeline.
Unsuccessfully predicted branches result in a four to five cycle branch-latency penalty in the super
pipeline.
March 2005
28
Datasheet
Document Number: 252479, Revision: 005
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