Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.7.1
EX_IOWAIT_N
The EX_IOWAIT_N signal is available to be shared by devices attached to Chip Selects 0 through
7 and is used as required by slow devices.
If the external device asserts EX_IOWAIT_N during the strobe phase of a read transfer, the
controller will hold in that phase until the EX_IOWAIT_N goes false. At that time, the controller
will immediately transition to the hold phase regardless of the setting of the programming
parameter (T3) for the strobe phase.
The EX_IOWAIT_N signal only affects the interface during the strobe phase of a read transfer. If
Chip Selects 4 through 7 are configured in HPI mode of operation, each chip select will have a
corresponding HRDY signal called EX_RDY. The polarity of the ready signal is programmable.
Chip Select 4 corresponds to EX_RDY signal 0 and Chip Select 7 corresponds to EX_RDY signal
3.
5.5.2.8
High-Speed, Serial Interfaces
High-Speed, Serial Timings
Figure 41.
T2
T4
T9
T1
T3
As Inputs:
hss_txclk/
hss_rxclk1
hss_(tx or rx)frame
(Positive edge)
hss_(tx or rx)frame
(Negative edge)
hss_ rxdata
(Positive edge)
Valid Data
hss_ rxdata
(Negative edge)
Valid Data
T5
T6
T7
T8
As Outputs:
hss_(tx or rx)frame
(Positive edge)
hss_(tx or rx)frame
(Negative edge)
hss_ txdata
(Positive edge)
Valid Data
hss_ txdata
(Negative edge)
Valid Data
A9594-01
Datasheet
March 2005
125
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
