Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.9
JTAG
Figure 42.
Boundary-Scan General Timings
T
T
bsch
bsel
JTG_TCK
JTG_TMS, JTG_TDI
T
bsis
T
bsih
JTG_TDO
T
bsoh
T
bsod
B0416-01
Figure 43.
Boundary-Scan Reset Timings
JTG_TRST_N
T
bsr
JTG_TMS
T
T
bsrs bsrh
A9597-01
Table 65.
Boundary-Scan Interface Timings Values
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units Notes
Tbscl
JTAG_TCK low time
JTAG_TCK high time
50
50
ns
ns
2
2
Tbsch
JTAG_TDI, JTAG_TMS setup time
to rising edge of JTAG_TCK
Tbsis
Tbsih
Tbsoh
10
10
ns
ns
ns
JTAG_TDI, JTAG_TMS hold time
from rising edge of JTAG_TCK
JTAG_TDO hold time after falling
edge of JTAG_TCK
1.5
1
1
JTAG_TDO clock to output from
falling edge of JTAG_TCK
Tbsod
Tbsr
40
ns
ns
ns
JTAG_TRST_N reset period
30
10
JTAG_TMS setup time to rising
edge of JTAG_TRST_N
Tbsrs
JTAG_TMS hold time from rising
edge of JTAG_TRST_N
Tbsrh
10
ns
Notes:
1.
2.
Tests completed with a TBD pF load to ground on JTAG_TDO.
JTAG_TCK may be stopped indefinitely in either the low or high phase.
Datasheet
March 2005
127
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
