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GWIXP425BDT 参数 Datasheet PDF下载

GWIXP425BDT图片预览
型号: GWIXP425BDT
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内容描述: 网络处理器Intel㈢ IXP42X产品线和IXC1100控制平面处理器 [Intel㈢ IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor]
分类和应用:
文件页数/大小: 134 页 / 1072 K
品牌: INTEL [ INTEL ]
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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor  
Table 62.  
HPI-16 Simplex Read Accesses Values  
Symbol  
Parameter  
Min. Max. Units  
Notes  
Cycles 1, 5, 6  
Cycles 5, 6  
Valid time that address is asserted on the line. The address is  
asserted at the same time as chip select.  
Tadd_setup  
11  
45  
Delay from chip select being active and the HDS1 data strobe  
being active.  
Tcs2hds1val  
3
4
4
4
5
5
Thds1_pulse Pulse width of the HDS1 data strobe.  
Cycles 2, 4, 5  
Cycles 3, 5, 6  
Data is valid from the time from of the falling edge of HDS1_N  
Tdata_setup  
to when the data is read.  
Time required between successive accesses on the  
expansion interface.  
Trecov  
2
17  
Cycles  
4, 6  
Notes:  
1.  
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T  
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the  
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to  
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-  
active.  
2.  
3.  
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T  
clocks for setup phase.  
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T  
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®  
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to  
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-  
active.  
4.  
5.  
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on  
the Expansion Bus interface.  
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or  
T3 until HRDY is de-active.  
6.  
7.  
One cycle is the period of the Expansion Bus clock.  
Timing tests were performed with a 70-pF capacitor to ground.  
Datasheet  
March 2005  
Document Number: 252479, Revision: 005  
121