Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 66.
Reset Timings Table Parameters
Symbol
Parameter
Min.
Typ.
Max.
Units
Note
Minimum time required to hold the
PWRON_RST_N at logic 0 state after
stable power has been applied to the
TRELEASE_PWRON_RST_N IXP42X product line and IXC1100 control
plane processors. When using a crystal
to drive the processors’ system clock.
500
ms
1
(OSC_IN and OSC_OUT)
Minimum time required to hold the
RESET_IN_N at logic 0 state after
PWRON_RST_N has been released to a
TRELEASE_RESET_IN_N
10
ns
logic 1 state. The RESET_IN_N signal
must be held low when the
PWRON_RST_N signal is held low.
Maximum time for PLL_LOCK signal to
drive to logic 1 after RESET_IN_N is
driven to logic 1 state. The boot
sequence does not occur until this period
is complete.
TPLL_LOCK
10
µs
ns
ns
Minimum time for the EX_ADDR signals
to drive the inputs prior to RESET_IN_N
being driven to logic 1 state. This is used
for sampling configuration information.
TEX_ADDR_SETUP
50
0
2
2
Minimum/maximum time for the
EX_ADDR signals to drive the inputs
prior to PLL_LOCK being driven to logic 1
state. This is used for sampling
configuration information.
TEX_ADDR_HOLD
20
Minimum time required to drive
RESET_IN_N signal to logic 0 in order to
cause a reset after the IXP42X product
line and IXC1100 control plane
processors has been in normal operation.
The power must remain stable and the
PWRON_RST_N signal must remain
stable.
TWARM_RESET
500
ns
Notes:
1.
TRELEASE_PWRON_RST_N is the time required for the internal oscillator to reach stability. When an
external oscillator is being used in place of a crystal, the 500-ms delay is not required.
The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a
programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals
must be active until PLL_LOCK is active.
2.
3.
PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is
asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks
after the watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.
5.6
Power Sequence
The 3.3-V I/O voltage (V
) must be powered up 1 µs before the core voltage (V ). The
CC
CCP
IXP42X product line and IXC1100 control plane processors’ core voltage (V ) must never
CC
become stable prior to the 3.3-V I/O voltage (V
). The V
, V
, and V
CCP
CCOSC
CCPLL1 CCPLL2
voltages follow the V power-up pattern. The V
follows the V
power-up pattern. The
CCP
CC
CCOSCP
value for T
must be at least 1 µs. The T
timing parameter is measured from
POWER_UP
POWER_UP
V
at 3.3 V and V at 1.3 V. There are no power-down requirements for the IXP42X product
CCP
CC
line and IXC1100 control plane processors.
Datasheet
March 2005
129
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
