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EPM1270GF100I4N 参数 Datasheet PDF下载

EPM1270GF100I4N图片预览
型号: EPM1270GF100I4N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100]
分类和应用: 输入元件可编程逻辑
文件页数/大小: 98 页 / 1060 K
品牌: INTEL [ INTEL ]
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I/O Structure  
I/O Blocks  
The IOEs are located in I/O blocks around the periphery of the MAX II  
device. There are up to seven IOEs per row I/O block (5 maximum in the  
EPM240 device) and up to four IOEs per column I/O block. Each column  
or row I/O block interfaces with its adjacent LAB and MultiTrack  
interconnect to distribute signals throughout the device. The row I/O  
blocks drive row, column, or DirectLink interconnects. The column I/O  
blocks drive column interconnects.  
Figure 2–20 shows how a row I/O block connects to the logic array.  
2–30  
Core Version a.b.c variable  
Altera Corporation  
August 2006  
MAX II Device Handbook, Volume 1  
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