I/O Structure
Figure 2–22. MAX II I/O Banks for EPM240 & EPM570
Notes (1), (2)
I/O Bank 1
I/O Bank 2
All I/O Banks Support
■ 3.3-V LVTTL/LVCMOS
■ 2.5-V LVTTL/LVCMOS
■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
Notes to Figure 2–22:
(1) Figure 2–22 is a top view of the silicon die.
(2) Figure 2–22 is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
The EPM1270 and EPM2210 devices support four I/O banks, as shown in
Figure 2–23. Each of these banks support all of the LVTTL and LVCMOS
standards shown in Table 2–4. PCI I/O is supported in Bank 3. Bank 3
supports the PCI clamping diode on inputs and PCI drive compliance on
outputs. You must use Bank 3 for designs requiring PCI compliant I/O
pins. The Quartus II software automatically places I/O pins in this bank
if assigned with the PCI I/O standard.
2–34
Core Version a.b.c variable
Altera Corporation
August 2006
MAX II Device Handbook, Volume 1