MAX II Architecture
Fast I/O Connection
A dedicated fast I/O connection from the adjacent LAB to the IOEs within
an I/O block provides faster output delays for clock-to-output and tPD
propagation delays. This connection exists for data output signals, not
output enable signals or input signals. Figures 2–20, 2–21, and 2–22
illustrate the fast I/O connection.
Figure 2–19. MAX II IOE Structure
Data_in Fast_out
Data_out OE
DEV_OE
Optional
PCI Clamp (1)
Programmable
Pull-Up
V
V
CCIO
CCIO
I/O Pin
Optional Bus-Hold
Circuit
Drive Strength Control
Open-Drain Output
Slew Control
Optional Schmitt
Trigger Input
Programmable
Input Delay
Note to Figure 2–19:
(1) Available in EPM1270 and EPM2210 devices only.
Altera Corporation
August 2006
Core Version a.b.c variable
2–29
MAX II Device Handbook, Volume 1
INTEL [ INTEL ]
