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EP4CE22E22I7N 参数 Datasheet PDF下载

EP4CE22E22I7N图片预览
型号: EP4CE22E22I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1395 CLBs, 472.5MHz, 22320-Cell, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, EQFP-144]
分类和应用: 时钟LTEPC可编程逻辑
文件页数/大小: 44 页 / 663 K
品牌: INTEL [ INTEL ]
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1–36  
Chapter 1: Cyclone IV Device Datasheet  
Switching Characteristics  
Table 1–44 and Table 1–45 list the IOE programmable delay for Cyclone IV GX  
devices.  
Table 1–44. IOE Programmable Delay on Column Pins for Cyclone IV GX Devices (1), (2)  
Max Offset  
Slow Corner  
C7 C8  
Number  
of  
Settings  
Paths  
Affected  
Min  
Offset  
Parameter  
Fast Corner  
C6 I7  
Unit  
C6  
I7  
Pad to I/O  
dataout to  
core  
Input delay from pin to  
internal cells  
7
8
2
0
0
0
1.313 1.209 2.184 2.336 2.451 2.387  
1.312 1.208 2.200 2.399 2.554 2.446  
0.438 0.404 0.751 0.825 0.886 0.839  
ns  
ns  
ns  
Input delay from pin to Pad to I/O  
input register  
input register  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
Input delay from  
dual-purpose clock pin clock  
to fan-out destinations network  
Pad to global  
12  
0
0.713 0.682 1.228  
1.41  
1.566 1.424  
ns  
Notes to Table 1–44:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.  
Table 1–45. IOE Programmable Delay on Row Pins for Cyclone IV GX Devices (1), (2)  
Max Offset  
Number  
Paths  
Affected  
Min  
Parameter  
of  
Fast Corner  
Slow Corner  
Unit  
Offset  
Settings  
C6 I7  
C6  
C7 C8  
I7  
Pad to I/O  
dataout to  
core  
Input delay from pin to  
internal cells  
7
8
2
0
0
0
1.314 1.210 2.209 2.398 2.526 2.443  
1.313 1.208 2.205 2.406 2.563 2.450  
0.461 0.421 0.789 0.869 0.933 0.884  
ns  
ns  
ns  
Input delay from pin to Pad to I/O  
input register  
input register  
I/O output  
register to  
pad  
Delay from output  
register to output pin  
Input delay from  
dual-purpose clock pin  
to fan-out destinations  
Pad to global  
clock network  
12  
0
0.712 0.682 1.225 1.407 1.562 1.421  
ns  
Notes to Table 1–45:  
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.  
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software  
Cyclone IV Device Handbook,  
Volume 3  
March 2016 Altera Corporation  
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