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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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1–34  
Chapter 1: Cyclone III Device Datasheet  
Document Revision History  
Table 1–40. Document Revision History (Part 3 of 3)  
Date  
Version  
Changes  
Corrected current unit in Tables 1-1, 1-12, and 1-14.  
Added Note (3) to Table 1-3.  
Updated Table 1-4 with ICCINT0, ICCA0, ICCD_PLL0, and ICCIO0 information.  
Updated Table 1-9 and added Note (2).  
Updated Table 1-19.  
Updated Table 1-22 and added Note (1).  
May 2007  
1.1  
Changed I/O standard from 1.5-V LVTTL/LVCMOS and 1.2-V LVTTL/LVCMOS to 1.5-V  
LVCMOS and 1.2-V LVCMOS in Tables 1-41, 1-42, 1-43, 1-44, and 1-45.  
Updated Table 1-43 with changes to LVPEC and LVDS and added Note (5).  
Updated Tables 1-46, 1-47, Tables 1-54 through 1-95, and Tables 1-98 through 1-111.  
Removed speed grade –6 from Tables 1-90 through 1-95, and from Tables 1-110 through  
1-111.  
Added a waveform (Receiver Input Waveform) in glossary under letter “R” (Table 1-112).  
March 2007  
1.0  
Initial release.  
Cyclone III Device Handbook  
Volume 2  
July 2012 Altera Corporation  
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