2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
(1, 11)
4.14 AC Characteristics—CE#-Controlled Write Operations
—
Extended Temperature
Prod
TBV-80
TBV-80
TBE-120
Sym
Parameter
VCC
Load
Notes
3.3 ±0.3 V(9) 5 V±10%(10)
50 pF 100 pF
Min Max Min Max
Unit
tAVAV
Write Cycle Time
110
0.8
0
80
0.45
0
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
tPHEL
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
Boot Block Lock Setup to CE# Going High
VPP Setup to CE# Going High
Address Setup to CE# Going High
Data Setup to CE# Going High
CE# Pulse Width
tWLEL
tPHHEH
tVPEH
tAVEH
tDVEH
tELEH
6,8
5,8
200
200
90
70
90
0
100
100
60
60
60
0
3
4
tEHDX
tEHAX
tEHWH
tEHEL
Data Hold Time from CE# High
Address Hold Time from CE# High
WE# Hold Time from CE# High
CE# Pulse Width High
4
3
0
0
0
0
20
6
20
6
tEHQV1
tEHQV2
tEHQV3
tEHQV4
tQVVL
tQVPH
tPHBR
Word/Byte Program Time
2,5
2,5,6
2,5
Erase Duration (Boot)
0.3
0.3
0.6
0
0.3
0.3
0.6
0
Erase Duration (Param)
s
Erase Duration (Main)
2,5
s
VPP Hold from Valid SRD
5,8
ns
ns
ns
RP# VHH Hold from Valid SRD
Boot-Block Lock Delay
6,8
0
0
7,8
200
100
NOTES:
See AC Characteristics—WE#-Controlled Write Operations for notes 1 through 10.
11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#
defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be
measured relative to the CE# waveform.
52
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INTEL [ INTEL ]
