E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid A . (Table 7)
IN
4. Refer to command definition table for valid D . (Table 7)
IN
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tPHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configuration (Figure 21), 3.6 V and 3.3 ± 0.3 V Standard Test component values.
10. See Test Configuration (Figure 21), 5 V Standard Test component values.
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SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
