E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
(1)
4.12 AC Characteristics—Read Only Operations —Extended Temperature
Prod
TBV-80
TBV-80
TBE-120
Symbol
Parameter
VCC
Load
Notes
3.3 ± 0.3 V(5)
50 pF
5 V ± 10%(6)
100 pF
Unit
Min
Max
Min
Max
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
Read Cycle Time
110
80
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
Address to Output Delay
CE# to Output Delay
RP# to Output Delay
OE# to Output Delay
CE# to Output in Low Z
CE# to Output in High Z
OE# to Output in Low Z
OE# to Output in High Z
110
110
0.8
65
80
80
2
0.45
40
2
3
3
3
3
3
0
0
0
0
0
0
45
45
25
25
Output Hold from Address, CE#,
or OE# Change, Whichever
Occurs First
tELFL
tELFH
0
0
CE# Low to BYTE# High or Low
3
ns
tAVFL
Address to BYTE# High or Low
BYTE# to Output Delay
3
5
5
ns
ns
tFLQV
tFHQV
tFLQZ
tPLPH
3,4
110
80
BYTE# Low to Output in High Z
Reset Pulse Width
3
7
45
30
60
ns
ns
ns
150
60
tPLQZ
RP# Low to Output High-Z
150
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on tCE
.
3. Sampled, but not 100% tested.
4.
tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A–1 becomes valid.
5. See Test Configuration (Figure 21), 3.6 V and 3.3 ± 0.3 V Standard Test component values.
6. See Test Configuration (Figure 21), 5 V Standard Test component values.
7. The specification tPLPH is the minimum time that RP# must be held low in order to product a valid reset of the device.
49
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
