28F320J5 and 28F640J5
Figure 10. Set Block Lock-Bit Flowchart
Start
Bus
Operation
Command
Comments
Data = 60H
Addr =Block Address (Block),
Device Address (Master)
Set Block/Master
Lock-Bit Setup
Write 60H,
Block/Device Address
Write
Write
Data = 01H (Block)
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Set Block or Master
Lock-Bit Confirm
Write 01H/F1H,
Block/Device Address
Read
Status Register Data
Read Status Register
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
0
SR.7 =
Repeat for subsequent lock-bit operations.
1
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations
Full Status
Check if Desired
Write FFH after the last lock-bit set operation to place device in read
array mode.
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Check SR.3
Read Status Register
Data (See Above)
Standby
1 = Programming Voltage Error
Detect
1
SR.3 =
Voltage Range Error
Check SR.1
1 = Device Protect RP# = V
IH
Standby
(Set Master Lock-Bit Operation)
RP# = VIH, Master Lock-Bit Is Set
(set Block Lock-Bit Operation)
0
SR. 1 =
0
1
1
1
Device Protect Error
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Standby
Command Sequence
Error
Check SR.4
1 = Set Lock-Bit Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command, in cases where multiple lock-bits are set before full
status is checked.
SR.4 =
0
Set Lock-Bit Error
If an error is detected, clear the status register before attempting retry
or other error recovery.
Set Lock-Bit
Successful
0606_11
36
Datasheet
INTEL [ INTEL ]
