28F320J5 and 28F640J5
3. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command
Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
4. Bus operations are defined in Table 3.
5. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 5 and Table 13.
QA = Query database Address.
PA = Address of memory location to be programmed.
6. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See Table 16 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.
7. The upper byte of the data bus (DQ –DQ ) duringcommand writes is a “Don’t Care” in x16 operation.
8
15
8. Followingthe Read Identifier Codes command, read operations access manufacturer, device, block lock, and
master lock codes. See Read Identifier Codes Command section for read identifier code data.
9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument.
Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =
000FH. The third and consecutive bus cycles, as determined by N, are for writingdata into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in
the sequence aborts the write to buffer operation. Please see Fig ure 6, “Write to Buffer Flowchart” on
page 32, for additional information.
11.Programmingthe write buffer to flash or initiatingthe erase operation does not begin until a confirm
command (D0h) is issued.
12.If the block is locked, RP# must be at V to enable block erase or program operations. Attempts to issue a
HH
block erase or program to a locked block while RP# is V will fail.
IH
13.Either 40H or 10H are recognized by the WSM as the byte/word program setup.
14.If the master lock-bit is set, RP# must be at V to set a block lock-bit. RP# must be at V to set the master
HH
HH
lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is V
.
IH
15.If the master lock-bit is set, RP# must be at V to clear block lock-bits. The clear block lock-bits operation
HH
simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command
can be done while RP# is V
.
IH
4.1
4.2
Read Array Command
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to
read array mode. This operation is also initiated by writing the Read Array command. The device
remains enabled for reads until another command is written. Once the internal WSM has started a
block erase, program, or lock-bit configuration, the device will not recognize the Read Array
command until the WSM completes its operation unless the WSM is suspended via an Erase
Suspend command. The Read Array command functions independently of the VPEN voltage and
RP# can be VIH or VHH
.
Read Query Mode Command
This section defines the data structure or “database” returned by the Common Flash Interface (CFI)
Query command. System software should parse this structure to gain critical information such as
block size, density, x8/x16, and electrical specifications. Once this information has been obtained,
the software will know which command sets to use to enable flash writes, block erases, and
otherwise control the flash component. The Query is part of an overall specification for multiple
command set and control interface descriptions called Common Flash Interface, or CFI.
18
Datasheet
INTEL [ INTEL ]
