Host Bridge/DRAM Controller Registers (D0:F0)
R
Bit
Access &
Default
Description
4
R/W
1b
82915G/82915GV/82915GL/82910GL GMCH:
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0 Device 2 Function 1 is disabled and hidden
1 = Bus 0 Device 2 Function 1 is enabled and visible
Note: Setting this bit to enabled when bit 3 is 0 has no meaning.
82915P/82915PL MCH:
Reserved.
3
R/W
1b
82915G/82915GV/82915GL/82910GL GMCH:
Internal Graphics Engine Function 0 (D2F0EN):
0 = Bus 0 Device 2 Function 0 is disabled and hidden
1 = Bus 0 Device 2 Function 0 is enabled and visible
82915P/82915PL MCH:
Reserved.
2
1
Reserved
R/W
1b
82915G/82915P/82915PL (G)MCH:
PCI Express* Port (D1EN):
Strap
dependent
0 = Bus 0 Device 1 Function 0 is disabled and hidden. This also gates PCI
Express internal clock (lgclk) and asserts PCI Express internal reset (lgrstb).
1 = Bus 0 Device 1 Function 0 is enabled and visible.
The SDVO Presence hardware strap determines default value. Device 1 is
disabled on Reset when the SDVO Presence strap (SDVO_CTLRDATA signal) is
sampled high, and is enabled otherwise.
82915GV/82915GL/82910GL GMCH:
Reserved.
0
RO
1b
Host Bridge: Bus 0 Device 0 Function 0 can not be disabled and is therefore
hardwired to 1.
80
Datasheet
INTEL [ INTEL ]
