Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.15
DMIBAR—Root Complex Register Range Base Address
(D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
4Ch
00000000h
R/W
Size:
32 bits
This is the base address for the Root Complex configuration space. This window of addresses
contains the Root Complex Register set for the PCI Express hierarchy associated with the
(G)MCH. There is no physical memory within this 4-KB window that can be addressed. The
4 KB that is reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space.
On reset, this register is disabled and must be enabled by writing a 1 to the DMIBAREN [Dev 0,
offset 54h, bit 29].
|
Bit
Access &
Default
Description
31:12
R/W
DMI Base Address: This field corresponds to bits 31 to 12 of the base address
0000 0h
DMI configuration space.
BIOS will program this register resulting in a base address for a 4-KB block of
contiguous memory address space. This register ensures that a naturally
aligned 4-KB space is allocated within total addressable memory space of
4 GB.
System software uses this base address to program the DMI register set.
Reserved
11:0
Datasheet
77
INTEL [ INTEL ]
