Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.17
DEVEN—Device Enable (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
54h
00000019h
R/W
Size:
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within the
(G)MCH.
Bit
Access &
Default
Description
31
R/W
0b
82915G/82915P/82915PL (G)MCH:
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and write transactions
proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:28 are
R/W with no functionality behind them.
1 = The PCIEXBAR register is enabled. Memory read and write transactions
whose address bits 31:28 match PCIEXBAR 31:28 will be translated to
configuration reads and writes within the (G)MCH. These translated cycles
are routed as shown in the table above.
82915GV/82915GL/82910GL GMCH:
Reserved.
30
29
Reserved
R/W
0b
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory.
1 = DMIBAR memory mapped accesses are claimed and decoded appropriately.
MCHBAR Enable (MCHBAREN):
28
R/W
0b
0 = MCHBAR is disabled and does not claim any memory.
1 = MCHBAR memory mapped accesses are claimed and decoded
appropriately.
27
R/W
0b
EPBAR Enable (EPBAREN):
0 = EPBAR is disabled and does not claim any memory.
1 = EPBAR memory mapped accesses are claimed and decoded appropriately.
Reserved
26:5
Datasheet
79
INTEL [ INTEL ]
