Host Bridge/DRAM Controller Registers (D0:F0)
R
4.1.21
PAM3—Programmable Attribute Map 3 (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
0
93h
00h
R/W
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h–
0D7FFFh.
Bit
Access &
Default
Description
7:6
5:4
Reserved
R/W
00b
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
00b
0D0000h–0D3FFFh Attribute (LOENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
84
Datasheet
INTEL [ INTEL ]
