Register Description
R
3.3.3
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and falls outside the range claimed
by the Host-PCI Express bridge (not between upper bound in device’s Subordinate Bus Number
register and lower bound in device’s Secondary Bus Number register), the (G)MCH would
generate a Type 1 DMI Configuration Cycle. This DMI configuration cycle will be sent over the
DMI.
If the cycle is forwarded to the Intel ICH6 via the DMI, the Intel ICH6 compares the non-zero
Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI-
to-PCI bridges to determine if the configuration cycle is meant for ICH6 PCI Express ports one of
the Intel ICH6’s devices, the DMI, or a downstream PCI bus.
Figure 3-3. DMI Type 0 Configuration Address Translation
Configuration Address
11
31
30
24 23
16 15
10
Function
8
7
2
1
0
Double
Word
Device
Number
Bus Number
1
Reserved
XX
DMI Type 0 Configuration Address Extension
OCF8h
OCFBh
OCFAh
OCF9h
11
31
30
24 23
16 15
10
Function
8
7
2
1
0
Double
Word
Device
Number
Bus Number
1
Reserved
00
DMI_Typ0_Config
Figure 3-4. DMI Type 1 Configuration Address Translation
Configuration Address
16 15
11
31
30
24 23
10
Function
8
7
2
1
0
Double
Word
Device
Number
Bus Number
1
Reserved
XX
DMI Type 1 Configuration Address Extension
OCFAh
OCF9h
OCF8h
OCFBh
11
0
31
30
24 23
16 15
10
Function
8
7
2 1
Double
Word
Device
Number
Bus Number
1
Reserved
00
DMI_Typ1_Config
Datasheet
59
INTEL [ INTEL ]
