Register Description
R
Figure 3-2. Register Organization (Representative of the Intel® 82915G GMCH)
PCI Express* Egress Port
(RCRB)
FFFh
Device 2 Configuration
Registers: Internal Graphics
VC1 (Isochronous) Port
Arbitration Controls
FFFh
0FFh
Unused
000h
DMI Root Complex Register
Block (RCRB)
FFFh
Mirror of bits needed by
graphics driver graphics
thermal controls
(G)MCH-ICH6 Serial Interface
(DMI) Controls:
Analog Controls Error
Reporting Controls VC Control
(Incl. VCp)
000h
FFFh
Device 1 Configuration
Registers: PCI Express X16
000h
PCI Express x16 Controls:
Analog Controls
Error Reporting Controls
VC Controls
PCI Express Address Range
0FFF FFFFh
Accessed only by PCI
Express enhanced access
mechanism. 4KB block
allocated for each potential
device in root hierarchy.
Hot Plug/Slot Controls
0FFh
Device Level Controls
000h
FFFh
Device 2 Range
Device 1 Range
Device 0 Range
Device 0 Configuration
Registers
0000 0000h
3FFFh
Device 0 MMIO Registers:
(G)MCH Control
Unused
Thermal Sensor PSB Analog
Controls (Rcomp+)
0FFh
000h
CH 0/1 Analog Controls
CH 0/1 Timing Controls
Ch 0/1 Throttling
Ch 0/1 Oranization Arviter
Controls
Device Level Controls, PAM
EPBAR
DMI BAR
PCIEXBAR
0000h
MCHBAR
Reg_Org_82915G
Note: Diagram not to scale
NOTES:
1. Very high level representation. Many details omitted.
2. Inter graphics memory mapped registers are not shown.
3. Only Device 1 use PCI Express extended configuration space.
4. Device 0 and Device 2 use only standard PCI configuration space.
5. Hex numbers represent address range size and not actual locations.
Table 3-1. Device Number Assignment for Internal (G)MCH Devices
(G)MCH Function
Device#
Host Bridge / DRAM Controller
Device 0
Device 1
Host-to-PCI Express* Bridge (virtual P2P) (Intel® 82915G/82915P/82915PL
(G)MCH only)
Internal Graphics Control (82915G/82915GV/82915GL/82910GL GMCH
only)
Device 2
Datasheet
57
INTEL [ INTEL ]
