Register Description
R
The (G)MCH contains the following PCI devices within a single physical component. The
configuration registers for the devices are mapped as devices residing on PCI bus 0.
• Device 0 – Host Bridge/DRAM Controller: Logically this appears as a PCI device residing
on PCI bus 0. Device 0 contains the standard PCI header registers, PCI Express base address
register, DRAM control (including thermal/throttling control), and configuration for the DMI
and other (G)MCH specific registers.
• Device 1– Host-PCI Express Bridge (82915G/82915P/82915PL (G)MCH only). Logically
this appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI
Express* Specification Revision 1.0a. Device 1 contains the standard PCI-to-PCI bridge
registers and the standard PCI Express/PCI configuration registers (including the PCI
Express memory address mapping). It also contains Isochronous and Virtual Channel
controls in the PCI Express extended configuration space.
• Device 2 – Internal Graphics Control (82915G/82915GV/82915GL/82910GL GMCH
only). Logically, this appears as a PCI device residing on PCI bus 0. Physically, device 2
contains the configuration registers for 3D, 2D, and display functions.
56
Datasheet
INTEL [ INTEL ]
