Register Description
R
3 Register Description
The (G)MCH contains two sets of software accessible registers, accessed via the processor I/O
address space: Control registers and internal configuration registers.
• Control registers are I/O mapped into the processor I/O space that control access to PCI and
PCI Express configuration space (see Section 3.4).
• Internal configuration registers residing within the (G)MCH are partitioned into three logical
device register sets (“logical” since they reside within a single physical device). The first
register set is dedicated to Host Bridge functionality (i.e. DRAM configuration, other chipset
operating parameters and optional features). The second register block is dedicated to the
82915G/82915P/82915PL (G)MCH Host-PCI Express Bridge functions (controls PCI
Express interface configurations and operating parameters). The third register block is for the
82915G/82915GV/82915GL/82910GL GMCH internal graphics functions.
The (G)MCH internal registers (I/O Mapped, Configuration and PCI Express Extended
Configuration registers) are accessible by the processor. The registers that reside within the lower
256 bytes of each device can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities,
with the exception of CONFIG_ADDRESS that can only be accessed as a DWord. All multi-byte
numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts
of the field). Registers that reside in bytes 256 through 4095 of each device may only be accessed
using memory mapped transactions in DWord (32-bit) quantities.
3.1
Register Terminology
The following table shows the register-related terminology that is used.
Item
Description
RO
Read Only bit(s). Writes to these bits have no effect.
RS/WC
Read Set / Write Clear bit(s). These bits are set to ‘1’ when read and then will continue
to remain set until written. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a
write of ‘0’ has no effect.
R/W
Read / Write bit(s). These bits can be read and written.
R/WC
Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A
write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect.
R/WC/S
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this
bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no
effect. Bits are not cleared by "warm" reset, but will be reset with a cold/complete reset
(for PCI Express* related bits a cold reset is “Power Good Reset” as defined in the PCI
Express* Specification).
R/W/L
R/W/S
Read / Write / Lockable bit(s). These bits can be read and written. Additionally there is a
bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field
from being writeable (bit field becomes Read Only).
Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a
cold reset is “Power Good Reset” as defined in the PCI Express* Specification).
Datasheet
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INTEL [ INTEL ]
