Signal Description
R
State During
RSTIN#
Assertion
State After RSTIN#
De-assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
S3
System
Memory
(DDR)
SWE_B#
SDQ_B[63:0]
O
I/O
O
TRI
TRI
TRI
TRI
TRI
LV
TRI
TRI
TRI
TRI
TRI
TRI
LV
TRI
SDM_B[7:0]
TRI
SDQS_B[7:0]
SDQS_B[7:0]#
SCKE_B[3:0]
SRCOMP0
I/O
I/O
O
TRI
TRI
LV
I/O
I/O
I
TRI
TRI
IN
TRI (after RCOMP)
TRI
TRI
IN
SRCOMP1
TRI (after RCOMP)
SM_SLEWIN[1:0]
SM_SLEWOU[1:0]
SMVREF[1:0]
SOCOMP[1:0]
IN
O
TRI
IN
TRI (after RCOMP)
TRI
IN
I
IN
I/O
TRI
TRI
TRI
DDR2: 40 Ω
resistor to
ground
Table 2-4. PCI Express* Graphics x16 Port Reset and S3 States
State During
S3
State After RSTIN#
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
De-assertion
Assertion
PCI
Express*-
Graphics
EXP_RXN[15:0]
EXP_RXP[15:0]
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_COMPO
EXP_COMPI
I/O
I/O
O
O
I
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
TRI
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
TRI
CMCT 1.0 V
TRI (after RCOMP)
TRI (after RCOMP)
I
TRI
TRI
Table 2-5. DMI Reset and S3 States
State During
RSTIN#
Assertion
S3
State After RSTIN#
De-assertion
Pull-up/ Pull-
down
Interface
Signal Name
I/O
DMI
DMI_RXN[3:0]
DMI_RXP[3:0]
DMI_TXN[3:0]
DMI_TXP[3:0]
I/O
I/O
O
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
CMCT 1.0 V
O
50
Datasheet
INTEL [ INTEL ]
