Signal Description
R
Table 2-6. Clocking Reset and S3 States
State During
State After
RSTIN# De-
assertion
S3
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
Assertion
HCLKN
I
I
I
I
I
I
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Clocks
HCLKP
GCLKN
GCLKP
DREFCLKN
DREFCLKP
Table 2-7. MISC Reset and S3 States
State During
RSTIN#
Assertion
S3
State After RSTIN#
De-assertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
RSTIN#
I
I
IN
HV
IN
HV
IN
HV
Misc.
PWROK
EXTTS#
I
PU
PU
PU
BSEL[2:0]
I
TRI
TRI
TRI
MTYPE
I
TERM HV
TERM HV
PU
TERM HV
TERM HV
PU
TERM HV
TERM HV
PU
EXP_SLR
I
ICH_SYNC#
SDVO_CTRLCLK
SDVO_CTRLDATA
O
O
I/O
TRI
TRI
TRI
TERM PD
TRI
TERM PD
Table 2-8. DAC Reset and S3 States (Intel® 82915G/82915GV/82915GL/82910GL GMCH only)
State During
RSTIN#
Assertion
S3
State After RSTIN#
Deassertion
Pull-up/
Pull-down
Interface
Signal Name
I/O
HSYNC
O
O
O
O
O
O
O
O
O
LV
LV
LV
LV
DAC
VSYNC
RED
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
RED#
TRI
GREEN
GREEN#
BLUE
TRI
TRI
TRI
BLUE#
REFSET
TRI
0.5* VCCA_DAC
255 Ω 1%
Resistor to
Ground
DDC_CLK
I/O
I/O
IN
IN
IN
IN
IN
IN
DDC_DATA
§
Datasheet
51
INTEL [ INTEL ]
