Signal Description
R
2.2
DDR/DDR2 DRAM Channel A Interface
Note that the 82910GL, 82915GL, and 82915PL (G)MCH only supports DDR DRAM.
Signal Name
Type
Description
SCLK_A[5:0]
O
SSTL-
2/1.8
SDRAM Differential Clock: (3 per DIMM). SCLK_Ax and its
complement SCLK_Ax# signal make a differential clock pair output. The
crossing of the positive edge of SCLK_Ax and the negative edge of its
complement SCLK_Ax# are used to sample the command and control
signals on the SDRAM.
SCLK_A[5:0]#
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
O
SSTL-
2/1.8
SDRAM Complementary Differential Clock: (3 per DIMM) These are
the complementary differential DDR/DDR2 clock signals.
O
SSTL-
2/1.8
Chip Select: (1 per Rank) These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank.
O
SSTL-
2/1.8
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM
O
Bank Select: These signals define which banks are selected within each
SSTL-
2/1.8
SDRAM rank
DDR2: 1-Gb technology is 8 banks.
DDR: 1-Gb technology is 4 banks. SBS_A[2] is not used.
SRAS_A#
SCAS_A#
SWE_A#
O
SSTL-
2/1.8
Row Address Strobe: This signal is used with SCAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
O
SSTL-
2/1.8
Column Address Strobe: This signal is used with SRAS_A# and
SWE_A# (along with SCS_A#) to define the SDRAM commands.
O
Write Enable: This signal is used with SCAS_A# and SRAS_A# (along
SSTL-
2/1.8
with SCS_A#) to define the SDRAM commands.
SDQ_A[63:0]
I/O
SSTL-
2/1.8
2x
Data Lines: SDQ_A signals interface to the SDRAM data bus.
SDM_A[7:0]
O
Data Mask: When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one SDM_Ax signal for
every data byte lane.
SSTL-
2/1.8
2X
SDQS_A[7:0]
I/O
SSTL-
2/1.8
2x
Data Strobes: For DDR, the rising and falling edges of SDQS_Ax are
used for capturing data during read and write transactions. For DDR2,
SDQS_Ax and its complement SDQS_Ax# signal make up a differential
strobe pair. The data is captured at the crossing point of SDQS_Ax and
its complement SDQS_Ax# during read and write transactions.
SDQS_A[7:0]#
I/O
SSTL-1.8
2x
Data Strobe Complements (DDR2 only): These signals are the
complementary DDR2 strobe signals.
38
Datasheet
INTEL [ INTEL ]
