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82915GV 参数 Datasheet PDF下载

82915GV图片预览
型号: 82915GV
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 426 页 / 3241 K
品牌: INTEL [ INTEL ]
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Signal Description  
R
2.1  
Host Interface Signals  
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination  
voltage of the Host Bus (VTT).  
Signal Name  
Type  
Description  
HADS#  
I/O  
Address Strobe: The processor bus owner asserts HADS# to indicate the  
first of two cycles of a request phase. The (G)MCH can assert this signal for  
snoop cycles and interrupt messages.  
GTL+  
HBNR#  
HBPRI#  
I/O  
Block Next Request: This signal is used to block the current request bus  
owner from issuing new requests. This signal is used to dynamically control  
the processor bus pipeline depth.  
GTL+  
O
Priority Agent Bus Request: The (G)MCH is the only Priority Agent on the  
processor bus. It asserts this signal to obtain the ownership of the address  
bus. This signal has priority over symmetric bus requests and will cause the  
current symmetric owner to stop issuing new transactions unless the  
HLOCK# signal was asserted.  
GTL+  
HBREQ0#  
I/O  
Bus Request 0: The (G)MCH pulls the processor’s bus HBREQ0# signal  
low during HCPURST#. The processor samples this signal on the active-to-  
inactive transition of HCPURST#. The minimum setup time for this signal is  
4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is  
20 HCLKs. HBREQ0# should be tristated after the hold time requirement  
has been satisfied.  
GTL+  
HCPURST#  
O
CPU Reset: The HCPURST# pin is an output from the (G)MCH. The  
(G)MCH asserts HCPURST# while RSTIN# is asserted and for  
approximately 1 ms after RSTIN# is de-asserted. The HCPURST# allows  
the processors to begin execution in a known state.  
GTL+  
Note that the Intel® ICH6 must provide processor frequency select strap set-  
up and hold times around HCPURST#. This requires strict synchronization  
between (G)MCH HCPURST# de-assertion and the Intel® ICH6 driving the  
straps.  
HDBSY#  
I/O  
GTL+  
O
Data Bus Busy: This signal is used by the data bus owner to hold the data  
bus for transfers requiring more than one cycle.  
HDEFER#  
Defer: Signals that the (G)MCH will terminate the transaction currently  
being snooped with either a deferred response or with a retry response.  
GTL+  
HDINV[3:0]#  
I/O  
Dynamic Bus Inversion: Driven along with the HD[63:0] signals. Indicates  
if the associated signals are inverted or not. HDINV[3:0]# are asserted such  
that the number of data bits driven electrically low (low voltage) within the  
corresponding 16 bit group never exceeds 8.  
GTL+  
HDINVx#  
Data Bits  
HDINV3#  
HDINV2#  
HDINV1#  
HDINV0#  
HD[63:48]  
HD[47:32]  
HD[31:16]  
HD[15:0]  
Datasheet  
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