Signal Description
R
Figure 2-1. Intel® (G)MCH Signal Interface Diagram
HA[31:3]#
HD[63:0]
HADS#
HSYNC
VSYNC
Intel®
RED, RED#
GREEN, GREEN#
BLUE, BLUE#
REFSET
DDC_CLK
DDC_DATA
82915G/
82915GV/
82910GL
Only
HBNR#
Analog
Display
HBPRI#
HDBSY#
HDEFER#
HDRDY#
HEDRDY#
HHIT#
SDVOB_GREEN-, SDVOB_GREEN+
SDVOB_BLUE-, SDVOB_BLUE+
SDVOC_RED- / SDVOB_ALPHA-,
SDVOC_RED+ / SDVOB_ALPHA+
SDVOC_GREEN-, SDVOC_GREEN+
SDVOC_BLUE-, SDVOC_BLUE+
SDVOC_CLK-, SDVOC_CLK+
SDVO_TVCLKIN-, SDVO_TVCLKIN,
SDVOB_INT-, SDVOB_INT+
SDVOC_INT-, SDVOC_INT+
SDVO_STALL-, SDVO_STALL+
SDVO_CTRLCLK
HHITM#
Processor
HLOCK#
System
HREQ[4:0]#
Bus
HPCREQ#
Interface
HTRDY#
HRS[2:0]#
HCPURST#
HBREQ0#
HDINV[3:0]#
Intel®
SDVO
Device
Interface1
Intel®
82915G/
82915GV/
82910GL
Only
HADSTB[1:0]#
HDSTBP[3:0]#, HDSTBN[3:0]#
BSEL[2:0]
SDVO_CTRLDATA
HRCOMP
HSCOMP
HSWING
HVREF
PCI
Express
x16
Graphics
Port
EXP_RXN[15:0], EXP_RXP[15:0]
EXP_TXN[15:0], EXP_TXP[15:0]
EXP_COMPO
EXP_COMPI
EXP_SLR
Intel®
82915G/
82915P
Only
SCS_A[3:0]#
SMA_A[13:0]
SBS_A[2:0]
SRAS_A#
SCAS_A#
SWE_A#
SDQ_A[63:0]
System
Memory2
HCLKP, HCLKN
GCLKP, GCLKN
DREFCLKN, DREFCLKP
RSTIN#
PWROK
EXTTS#
BSEL[2:0]
MTYPE
ICH_SYNC#
DDR/
DDR2
Channel
A
Clocks,
Reset, and
Misc.
SDM_A[7:0]
SDQS_A[7:0], SDQS_A[7:0]#
SCKE_A[3:0]
SCLK_A[5:0], SCLK_A[5:0]#
SODT_A[3:0]
SCS_B[3:0]#
SMA_B[13:0]
SBS_B[2:0]
SRAS_B#
SCAS_B#
SWE_B#
Direct
Media
Interface
System
DMI_RXP[3:0], DMI_RXN[3:0]
DMI_TXP[3:0], DMI_TXN[3:0]
Memory2
DDR/
DDR2
Channel
B
SDQ_B[63:0]
SDM_B[7:0]
SDQS_B[7:0], SDQS_B[7:0]#
SCKE_B[3:0]
SCLK_B[5:0], SCLK_B[5:0]#
SODT_B[3:0]
VCC
VTT
VCC_EXP
VCCSM
VCC2
Voltage
Reference,
and Power
VCCA_EXPPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_SMPLL
SRCOMP[1:0]
SOCOMP[1:0]
SM_SLEWIN[1:0]
SM_SLEWOUT[1:0]
SMVREF[1:0]
System
Memory2
VSS
Intel®
DDR/DDR2
Ref./ Comp.
82915G/
82915GV/
82910GL
Only
VCCA_DAC
VSSA_DAC
Note:
1. SDVO signals on the 82915G GMCH are multiplexed with the PCI Express x16 Graphics Port signals.
2. The 82910GL GMCH only supports DDR (not DDR2).
Signal_Info
34
Datasheet
INTEL [ INTEL ]
