Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.18
PMLIMIT1—Prefetchable Memory Limit Address (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
26h
0000h
RO, R/W
16 bits
Size:
This register, in conjunction with the corresponding Upper Limit Address register, controls the
processor-to-PCI Express Graphics prefetchable memory access routing based on the following
formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-
bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to
address bits A[39:32] of the 40-bit address. The configuration software must initialize this
register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh.
Thus, the top of the defined memory address range will be at the top of a 1-MB aligned memory
block. Note that prefetchable memory range is supported to allow segregation by the
configuration software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Bit
15:4
3:0
Access &
Default
Description
R/W
000h
Prefetchable Memory Address Limit (PMLIMIT): This field corresponds to
A[31:20] of the upper limit of the address range passed to PCI Express*.
RO
0h
64-bit Address Support: This field indicates the bridge supports only 32 bit
addresses.
8.1.19
CAPPTR1—Capabilities Pointer (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
34h
88h
RO
8 bits
Size:
The capabilities pointer provides the address offset to the location of the first entry in this
device’s linked list of capabilities.
Bit
Access &
Default
Description
7:0
RO
First Capability (CAPPTR1): The first capability in the list is the Subsystem ID
88h
and Subsystem Vendor ID Capability.
140
Datasheet
INTEL [ INTEL ]
