MCHBAR Registers
R
5.1.16
5.1.17
5.1.18
5.1.19
5.1.20
C1DRA2—Channel B DRAM Rank 2,3 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
189h
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRA0.
C1DCLKDIS—Channel B DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
18Ch
00h
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DCLKDIS.
C1BNKARC—Channel B Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
18Eh
0000h
R/W
Size:
16 bits
The operation of this register is detailed in the description for register C0BNKARC.
C1DRT1—Channel B DRAM Timing Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
194h
900122h
R/W
Size:
32 bits
The operation of this register is detailed in the description for register C0DRT1.
C1DRC0—Channel B DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
MCHBAR
1A0h
00000000h
R/W
Size:
32 bits
The operation of this register is detailed in the description for register C0DRC0.
Datasheet
107
INTEL [ INTEL ]
