MCHBAR Registers
R
Bit
Access &
Default
Description
6:4
R/W
DRAM RAS to CAS Delay (tRCD). This bit controls the number of clocks inserted
010b
between a row activate command and a read or write command to that row.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
Reserved
3
2:0
R/W
010b
DRAM RAS Precharge (tRP). This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same rank.
000 = 2 DRAM clocks
001 = 3 DRAM clocks
010 = 4 DRAM clocks
011 = 5 DRAM clocks
100 – 111 = Reserved
Datasheet
103
INTEL [ INTEL ]
